1. Field of the Invention
The present invention relates to a verification device for verifying whether a semiconductor integrated circuit operates normally or not, a verification method of the semiconductor integrated circuit, and computer readable medium storing verification program of the semiconductor integrated circuit. More particularly, the present invention relates to a verification device of semiconductor integrated circuit for executing assertion based verification, a verification method of the same, and a computer readable medium storing a verification program of the same.
2. Background Art
Recently, various verification devices of semiconductor integrated circuit are known, including, for example, a verification device of semiconductor integrated circuit for verifying by using verification language description such as assertion description (see Japanese Patent Application Laid-Open No. 2006-53813).
In this verification device, possible causes of failure in verification result include description error in circuit description, description error in verification language description, abnormal action due to combination of input signals prohibited in the specification, and shortage of preliminary condition in verification language description.
In a general verification device, an arbitrary one type of waveform is issued as failure information out of the circuit transition state causing failure. The verification inspector repeats trial and error for identifying the cause of failure from the four causes mentioned above on the basis of this failure information. It hence takes a tremendous time in verification of semiconductor integrated circuit.
In particular, in the case of a formal tool, since verification is required to cover all combinations of input signals by using a mathematical technique, lots of failure information occur due to abnormal action and shortage of preliminary conditions. Although such failure information is actually a meaningless information (hereinafter, referred to as “false error”), the verification inspector must eliminate all these false errors. For example, if the specification defines, “six signals of request system are one hot (permissible if all are 0),” in the event of six types of 1-bit request, 57 patterns out of 64 patterns (26 signals), that is, failure information of combination of 89% of signals is false error. It is extremely inefficient for the verification inspector to conduct trial and error in such event.